1. Field of the Invention
The present invention relates to a switching power supply device control circuit and a switching power supply device, and in particular to a switching power supply device control circuit, and a switching power supply device, wherein noise generation is reduced by giving jitter (frequency diffusion) to a switching frequency.
2. Description of the Background Art
A switching power supply device can convert a commercial alternating current voltage to an optional direct current voltage and output the direct current voltage, has a lower number of parts, and can also respond to a wide input voltage range. For example, a flyback type whose output voltage is isolated from a commercial power source is known.
FIG. 10 is a circuit diagram showing a typical configuration example of a flyback type switching power supply device.
The flyback type switching power supply device 100 has a control IC 8 which is a control circuit for pulse width modulation (PWM) control, and includes at least a transformer T, a diode 19, a capacitor 20, and a switching element, which are in FIG. 10. As the switching element, a metal oxide semiconductor field effect transistor (MOSFET) 17 is used here.
A commercial alternating current power source 1 is supplied to a diode bridge 4, via a common mode choke coil 2 and X capacitor 3 which configure an input noise filter, and is full-wave rectified by the diode bridge 4.
A capacitor 5, provided between the diode bridge 4 and the ground, has the function of holding the input voltage for stably supplying energy to the output and the function of absorbing switching noise generated due to the switching operation by the MOSFET 17. Also, a diode 6 half-wave rectifies and supplies the alternating current power source 1 to the VH terminal of the control IC 8 via a current limiting resistance 7. An input current to the VH terminal is limited by the current limiting resistance 7.
A thermistor 9 is connected to the LAT terminal of the control IC 8, thus providing overheat latch protection to the control IC 8. Also, the voltage of a sense resistance 12 is input into the CS terminal of the control IC 8 via a noise filter formed of a capacitor 10 and resistance 11.
The VCC terminal of the control IC 8 is connected to one end of a capacitor 13 and connected to an auxiliary winding 15 of the transformer T via a diode 14. The capacitor 13 holds a power supply voltage supplied to the control IC 8 when the PWM control is in operation. Also, the diode 14 is for supplying the voltage to the VCC terminal from the auxiliary winding 15 after a start.
One end of a primary winding 16 of the transformer T is connected to the capacitor 5, and the other end is connected to the drain terminal of the MOSFET 17. Also, the source terminal of the MOSFET 17 is grounded via the sense resistance 12, and a drain current Ids flowing through the MOSFET 17 is detected by the sense resistance 12. That is, the on-current of the MOSFET 17 is converted in the sense resistance 12 to a voltage signal proportional to the on-current, and the voltage signal (a current detection signal) is input into the CS terminal of the control IC 8 via the noise filter.
One end of a secondary winding 18 of the transformer T is connected to the diode 19, and furthermore, is grounded via the capacitor 20. The voltage of the capacitor 20 is an output voltage supplied to a load 25, and information on the voltage is sent from the secondary side to the primary side by a photo coupler 21. The photo coupler 21 is connected in series to a shunt regulator 22, the connection point of resistances 23 and 24 which divide the output voltage is connected to the shunt regulator 22, and the divided voltage value of the output voltage and an unshown reference voltage are compared by the shunt regulator 22. As a result of this, error information of the secondary side output voltage relative to the reference voltage is converted to a current signal by the shunt regulator 22, the current signal flows to an LED configuring the photo coupler 21 and is converted to an optical signal, the optical signal is transmitted to a phototransistor configuring the photo coupler 21, and load information is sent to the primary side.
In the switching power supply device 100 configured using the control IC 8 for PWM control, the voltage to which the alternating current input voltage is rectified is converted to a predetermined direct current voltage via the transformer T by controlling the switching operation of the MOSFET 17.
In the control IC 8 configured of an IC circuit, the load information output to the load 25 on the secondary side of the transformer T is detected by being fed back to the FB terminal of the control IC 8 via the shunt regulator 22 and photo coupler 21, as heretofore described.
Also, the drain current Ids of the MOSFET 17 is converted to a voltage by the sense resistance 12, and the voltage is detected at the CS terminal of the control IC 8. By determining the output signal from the OUT terminal by comparing an FB terminal voltage with a CS terminal voltage directly or indirectly, it is possible to PWM control a switching power source by variably controlling the on-width of the MOSFET 17, and thereby possible to adjust the power supplied to the secondary side load 25.
FIG. 11 is a block diagram showing a circuit configuration example of the control IC.
In the control IC 8, a start circuit 31 supplies a current to the VCC terminal from the VH terminal when starting, and when the alternating current power source 1 is applied, a current flows from the VH terminal through the start circuit 31 to the VCC terminal, in the control IC 8. By so doing, the capacitor 13 externally connected to the VCC terminal is charged, and the voltage value of the capacitor 13 rises.
A low voltage malfunction protection circuit (UVLO) 32 is connected to the VCC terminal and a reference power source V1. In the low voltage malfunction protection circuit 32, when the voltage value of the VCC terminal becomes equal to or more than the reference power source V1, a UVLO signal which is the output of the low voltage malfunction protection circuit 32 turns to Low (L) level, an internal power supply circuit 33 starts, and a power supply is carried out on each circuit in the control IC 8. On the other hand, while a VCC terminal voltage is low, the low voltage malfunction protection circuit 32 turns the UVLO signal to High (H) level and stops the operation of the control IC 8.
An oscillator (OSC) 34 is connected to the FB terminal, and a frequency modulation function which carries out frequency diffusion to reduce electromagnetic interference (EMI) noise generated in the switching operation of the MOSFET 17 is incorporated in the oscillator 34. The oscillator 34, which determines the switching frequency of the MOSFET 17 from the control IC 8, also has the function of lowering an oscillation frequency when under light load, apart from the frequency modulation function, and outputs an oscillation signal (a duty max signal) Dmax.
The oscillation signal Dmax being a signal whose H level time is long and which turns to L level for just a short time for each cycle, the cycle is the switching cycle of the switching power source, and the ratio of the cycle to the H level time in the cycle gives the maximum time ratio (duty max) of the switching power source. Also, a slope compensation circuit 35, connected to the CS terminal, includes the function of preventing subharmonic oscillation to be described hereafter.
The input terminal of an FB comparator 36 is connected to the FB terminal and a reference power source V2. When the FB terminal voltage drops below the reference power source V2, the FB comparator 36 determines that load power is small, and stops the switching operation by outputting a clear signal CLR to a one-shot circuit 37 at the stage subsequent to the FB comparator 36. Also, when the FB terminal voltage is higher than the reference power source V2, the FB comparator 36 starts the switching operation. By so doing, the FB comparator 36 realizes a burst operation which temporarily stops the switching operation when under light load.
The one-shot circuit 37, by being triggered when the oscillation signal Dmax of the oscillator 34 rises, generates a set pulse to be supplied to an RS flip-flop 38 at the subsequent stage. Also, the set pulse is also a blanking signal which prevents the MOSFET 17 from turning off erroneously due to noise generated at the CS terminal when the MOSFET 17 turns on. The one-shot circuit 37, while the clear signal CLR of H level is being input thereinto, does not output the set pulse to be supplied to the RS flip-flop 38.
The RS flip-flop 38 generates a PWM signal in conjunction with an OR gate 39 and an AND gate 40. That is, the OR gate 39 generates a logical sum (OR) signal from two output signals, the output signal of the one-shot circuit 37 and the output signal of the RS flip-flop 38, which are input into the OR gate 39.
Basically, the output signal of the OR gate 39 is the PWM signal, but furthermore, the AND gate 40 determines the maximum duty of the PWM signal based on the oscillation signal Dmax of the oscillator 34.
The UVLO signal output from the low voltage malfunction protection circuit 32 is supplied to a drive circuit (OUTPUT) 42 via an OR gate 41, thus controlling whether or not to allow an operation of the drive circuit 42. The drive circuit 42 controls switching of the gate of the MOSFET 17 using a switch signal Sout output from the drive circuit 42 via the OUT terminal. That is, when the VCC terminal voltage is low and the UVLO signal is H level, the output of the drive circuit 42 is turned off (a signal which turns off the MOSFET 17 is output). On the other hand, when the VCC terminal voltage is high, the UVLO signal is L level and the output signal of a latch circuit 49 is L level, the drive circuit 42 controls switching of the gate of the MOSFET 17.
A level shift circuit 43 has the function of level shifting the FB terminal voltage to a voltage range in which the FB terminal voltage can be input into a CS comparator 44, and the output signal of the level shift circuit 43 is supplied to the inverting input terminal (−) of the CS comparator 44. The output signal of the slope compensation circuit 35 is supplied to the non-inverting input terminal (+) of the CS comparator 44. An internal power source voltage is connected to the FB terminal via a resistance R0, and the resistance R0 is the load resistance (pull-up resistance) of the phototransistor configuring the photo coupler 21. Therefore, the magnitude of an error signal wherein the difference between a voltage applied to the load 25 connected to the switching power supply device 100 and the reference voltage is amplified is detected from a drop in the voltage from the internal power supply circuit 33 due to the resistance R0. The error signal is a signal indicating that the larger the value of the magnitude of the error signal, the heavier the load.
In the CS comparator 44, the CS terminal voltage provided with slope compensation for preventing the subharmonic oscillation, to be described hereafter, is compared with the level shifted FB terminal voltage, thus determining the off-timing of the MOSFET 17.
Also, an OCP comparator 45 which determines the overcurrent detection level of the MOSFET 17 is connected to the CS terminal of the control IC 8. In the OCP comparator 45, the non-inverting input terminal (+) thereof is connected to the CS terminal, and the inverting input terminal (−) is connected to a reference power source V3, thus determining the overcurrent detection level of the MOSFET 17.
Further, an off-signal from the CS comparator 44 and an off-signal from the OCP comparator 45 after a delay time is adjusted by a delay time control circuit 50 are both supplied to the reset terminal of the RS flip-flop 38 via an OR gate 46.
A current is supplied to the thermistor 9 from a current source 47 via the LAT terminal. An LAT comparator 48, connected to the LAT terminal and a reference power source V4, when detecting that the voltage of the LAT terminal (that is, the voltage of the thermistor 9) has dropped below the voltage of the reference power source V4, determines that there is an overheat condition, and outputs a set signal to be supplied to the latch circuit 49.
The latch circuit 49, upon receiving the set signal of the LAT comparator 48, outputs a latch signal Latch of H level to the OR gate 41 and an OR gate 51. By so doing, the drive circuit 42 is turned off, and the start circuit 31 is turned on. Also, the UVLO signal of the low voltage malfunction protection circuit 32 is supplied to the reset terminal of the latch circuit 49, and when the potential of the VCC terminal drops, a latch condition is extinguished.
When the internal power supply circuit 33 starts and the power source is supplied to the internal circuits, a voltage is applied to the phototransistor configuring the photo coupler 21 via the resistance R0 and FB terminal, and the FB terminal voltage rises.
When the FB terminal voltage signal becomes equal to or more than a certain voltage value, the oscillation signal Dmax is output from the oscillator 34, and the set pulse to be supplied to the RS flip-flop 38 is output from the one-shot circuit 37 which is triggered when the oscillation signal Dmax rises.
The set pulse is input into the OR gate 39 together with the output signal of the RS flip-flop 38. Further, the output signal of the OR gate 39, passing through the AND gate 40 and drive circuit 42 as the PWM signal, is output from the OUT terminal to the gate terminal of the MOSFET 17, turns to the switch signal Sout, and drives the MOSFET 17.
By so doing, the MOSFET 17 turns on when the oscillation Dmax rises. The reason for adopting the logical sum of the output signal of the RS flip-flop 38 and the set pulse from the one-shot circuit 37 is to prevent the RS flip-flop 38 from being reset due to noise generated at the CS terminal when the MOSFET 17 turns on and from turning off immediately after the MOSFET 17 turns on.
As the drain current Ids flows through the sense resistance 12 when the MOSFET 17 turns on, the voltage of the CS terminal of the control IC 8 rises. Further, when the voltage of the CS terminal, which is slope compensated by the slope compensation circuit 35 of the control IC 8, reaches a voltage to which the FB terminal voltage is level shifted by the level shift circuit 43, a reset signal is output from the CS comparator 44 to the RS flip-flop 38 via the OR gate 46.
As the output of the OR gate 39 turns to L level by the RS flip-flop 38 being reset (in normal operation, the set pulse from the one-shot circuit 37 is L level at this point), as a result of which the output of the AND gate 40 also turns to L level, and the MOSFET 17 turns off in response to the switch signal Sout.
Also, even though the load 25 connected to the switching power supply device is extremely heavy, and a voltage value fed back to the FB terminal of the control IC 8 falls out of a (high voltage side) control range, the voltage value of the CS terminal is compared with the reference power source V3 by the OCP comparator 45, and when the result is that the voltage value of the CS terminal is equal to or more than the reference power source V3, it is possible to turn off the MOSFET 17.
Before the voltage to which the FB terminal voltage is level shifted is compared with the CS terminal voltage by the CS comparator 44, the slope compensation wherein a slope compensation voltage proportional to the on-width of the MOSFET 17 is added to the CS terminal voltage by the slope compensation circuit 35 is performed on the CS terminal voltage.
In general, in the event that the MOSFET 17 is operating in steady state, the magnitude of the current flowing through the MOSFET 17 at the beginning of each switching cycle is constant. However, when the duty (an on-time ratio=the on-width/the switching cycle) of the MOSFET 17 is too large, the magnitude of the current is no longer constant, and the condition of the current flowing through the MOSFET 17 changes for each switching cycle. When this phenomenon occurs, the current flowing through the MOSFET 17 comes into a condition in which a switching frequency signal is superimposed on a low frequency signal.
Oscillation at this kind of low frequency is known as subharmonic oscillation, but the subharmonic oscillation has a condition under which the subharmonic oscillation occurs. The subharmonic oscillation can be prevented in such a way that the condition is prevented from being met by slope compensation wherein a monotonically increasing signal is superimposed on the CS terminal voltage.
Herein, in the switching power supply device 100, the oscillator 34 of the control IC 8 generates the oscillation signal Dmax for causing the switching operation of the MOSFET 17, and typically, 65 kHz, 25 kHz, and a frequency between these frequencies are used. That is, when the load 25 is a heavy load, the switching frequency operates fixed at 65 kHz, and the frequency is varied from 65 kHz to 25 kHz as the load 25 becomes lighter. When the frequency drops to 25 kHz, the frequency is fixed at 25 kHz, thus preventing the frequency from dropping to an audio frequency which causes a sounding of the transformer T. In this way, an operation frequency is reduced as the load becomes lighter, thereby enabling an increase in the efficiency of the switching power supply device 100.
Herein, when the switching frequency is fixed at, for example, 65 kHz, a high order harmonic with 65 kHz as a fundamental wave is generated at the same time, the high order harmonic is emitted to the outside of the switching power supply device 100 as radiated EMI and conducted EMI. As this kind of EMI noise affects the operation of other electronics, the reference of a required limit is set in order not to generate a certain amount or more of EMI noise. Hereafter, a discussion will be given of conducted EMI noise.
In the field of power electronics such as the switching power supply device 100, jitter (frequency diffusion) is used as a method of reducing conducted EMI noise (for example, refer to JP-A-2014-204544).
FIGS. 12A and 12B are diagrams showing a difference in noise energy between the existence and non-existence of jitter, wherein the horizontal axis indicates the frequency, and the vertical axis indicates the noise energy. Also, FIG. 12A shows a case in which there is no jitter, and FIG. 12B shows a case in which there is jitter. FIG. 12B shows the case of center diffusion wherein the frequency is diffused in a range of ±Δf centered on a frequency fs with no jitter.
In the case of no jitter, noise energy concentrates in the position at the frequency fs, exhibiting a high peak, but the noise energy disperses by diffusing the frequency in the range of ±Δf centered on the frequency fs, and the average value of the noise energy decreases. Therefore, even though the peak exceeds the required limit when there is no jitter, the peak can be set to equal to or less than the required limit when there is jitter.
FIG. 13 is a diagram showing a noise level attenuation effect when the switching frequency is diffused. In FIG. 13, the horizontal axis indicates the diffusion width, while the vertical axis indicates the attenuation, and noise attenuation when the frequency fs of the fundamental wave is 65 kHz and a resolution bandwidth RBW which is a measurement frequency width is 9 kHz, is shown.
According to FIG. 13, attenuation S shows that the wider the diffusion width, the larger the attenuation S, and the greater the noise level attenuation effect. Also, the attenuation S at this time can be expressed by the following equation (for example, refer to JP-A-2008-5682 (Mathematical 2)).S=10×log(2×δ×fs/RBW)=10×log(2Δf/RBW)Herein, δ is a diffusion rate (%), fs is an operation frequency (Hz), Δf is a one-sided diffusion width (=fs×δ) (Hz), and RBW is a resolution bandwidth (Hz). According to the equation of the attenuation S, it is represented that the larger the ratio of the diffusion width (2Δf) to the resolution bandwidth RBW, the greater the attenuation effect.
In the meantime, as the measurement frequency range of EMI noise is defined, in the existing standard of conducted EMI, as being from 150 kHz to 30 MHz, there is a need to take a harmonic of 150 kHz or more into account as for the attenuation effect. According to FIG. 13, in order to obtain an attenuation of 3 dB or more, it is necessary to secure 20 kHz or more as the diffusion width (2Δf). Herein, a description will be given of a case in which the diffusion width is fixed at a certain rate (herein, ±7%) with respect to the fundamental switching operation frequencies fs of 65 kHz and 25 kHz. That is, the switching power supply device 100 operates at 65 kHz±4.55 kHz when under heavy load, and operates at 25 kHz±1.75 kHz when under light load.
As an order n=3 applies to the harmonic of 150 kHz or more at 65 kHz±4.55 kHz, the third order harmonic frequency is 3×(65 kHz±4.55 kHz)=195 kHz±13.65 kHz, and the diffusion width is 27.3 kHz. As the harmonic is such that the higher the order, the smaller the energy, it is not necessary to take into account the attenuation of a fourth or higher order harmonic in the event that the third order harmonic is below the EMI limit.
As an order n=6 applies to the harmonic of 150 kHz or more at 25 kHz±1.75 kHz, the sixth order harmonic frequency is 6×(25 kHz±1.75 kHz)=150 kHz±10.5 kHz, and the diffusion width is 21 kHz.
Therefore, by setting the diffusion width at ±7% with respect to the switching operation frequencies fs of 65 kHz and 25 kHz, it is possible to secure a diffusion width of 25 kHz or more in the measurement frequency range of EMI noise, and thus possible to obtain an attenuation of 3 dB or more.
FIG. 14 is a circuit diagram showing a configuration example of an oscillator having a jitter control circuit which carries out frequency diffusion, and FIG. 15 is a circuit diagram showing a configuration example of the jitter control circuit.
The oscillator 34 includes a buffer amplifier 61, which detects the feedback voltage FB, and an amplifier 62, which controls a current flowing through a transistor (an n-channel MOS-FET) N1 in response to the output of the buffer amplifier 61, as shown in FIG. 14. The transistor N1 is connected to a current mirror circuit formed of transistors (n-channel MOS-FETs) P1 and P2, and the current flowing through the transistor N1 is the input current of the current mirror circuit. The output current of the current mirror circuit is given to a transistor N2 connected to the drain terminal of the transistor P2 which is the output terminal of the current mirror circuit, and is used to control a current flowing through a transistor N5. Furthermore, the output current of the current mirror circuit is used to control a current flowing through a transistor P4 via a transistor N3 and transistor P3.
The transistors P4 and N5 are connected in series via transistors P5 and N4 which are complementarily controlled on/off. Further, a capacitor C is connected to the series connection point of the transistors P5 and N4. The transistor P5 assumes the role of charging the capacitor C with the current flowing through the transistor P4 when the transistor P5 is in on-operation. Also, the transistor N4 assumes the role of charging the capacitor C with the current flowing through the transistor N5 when the transistor N4 is in on-operation.
A hysteresis comparator 63 compares the charge/discharge voltage of the capacitor C and a predetermined reference voltage Vref (which is actually formed of two reference voltages, a high side reference voltage VrefH and a low side reference voltage VrefL, because of a hysteresis comparator), and an inverter 64 inverts the output of the hysteresis comparator 63 and generates the oscillation signal Dmax for driving the MOSFET 17 on/off. Also, at the same time, the output of the hysteresis comparator 63 is used as a control signal which complementarily drives the transistors P5 and N4 on/off and a clock signal which defines the operation of a jitter control circuit 70.
The jitter control circuit 70 includes a plurality (four) of transistors P11, P12, P13, and P14, which form current mirror circuits in parallel with the transistor P1, and transistors P15, P16, P17, and P18, which are connected in series with the respective transistors P11, P12, P13, and P14, as shown in FIG. 15. The transistors P15, P16, P17, and P18 assume the role of, by being controlled on/off upon receiving outputs Q0, Q1, Q2, and Q3 of a frequency divider and counter 71, selectively extracting currents flowing through the transistors P11, P12, P13, and P14, and applying the current to the drain current of the transistor N2.
The respective currents flowing through the transistors P11, P12, P13, and P14 are set as, for example, 11, 12 (=2·I1), 13 (=2·I2=4·I1), 14 (=2·I3=4·I2=8·I1). These current ratios are set by changing the gate width/gate length of the transistors P11, P12, P13, and P14 forming the respective current mirror circuits with the transistor P1.
Incidentally, the frequency divider and counter 71 divides the output of the hysteresis comparator 63 and performs a counting operation. Further, the frequency divider and counter 71 counts the number resulting from the counting operation and changes the outputs Q0, Q1, Q2, and Q3 in order in, for example, a range of [0000] to [1111]. By so doing, the transistors P15, P16, P17, and P18 are selectively controlled on/off. Further, the currents flowing through the transistors P11, P12, P13, and P14 are selectively output by a selective on-operation of the transistors P15, P16, P17, and P18.
As a result of this, an output current b of the jitter control circuit 70 changes step by step, and the output current b is applied to the transistor N2. Further, a step-by-step change is given to a current which charges the capacitor C, and a cyclic change is given to a time for which the capacitor C is charged to the reference voltage Vref. As a result of this, cyclic fluctuations with a certain width are given to the frequency of a pulse signal output via the hysteresis comparator 63. This kind of oscillation frequency control is jitter control of the switching frequency which drives the MOSFET 17. Further, EMI noise generated as a result of switching of the MOSFET 17 is diffused in frequency by the jitter control, thereby reducing the EMI noise.
In the meantime, it is under consideration that the existing conducted EMI standard (the measurement frequency range exceeds 150 kHz) is defined so as to expand the EMI noise measurement frequency range to a low frequency of 150 kHz or less and thus prevent conducted EMI noise from being generated even in a lower measurement frequency range. When the measurement frequency range expands, the switching operation frequency, that is, the frequency of a fundamental wave having largest noise energy falls in the measurement frequency range, and it is necessary to take measures against noise from the fundamental wave of the switching frequency (for example, 65 kHz). When attempting to suppress this with an EMI filter, there is the problem of the possibility that the constants of the inductor and capacitor become larger due to the low frequency, as a result of which the size of parts increases, and that the size of the switching power supply device increases and, eventually, the cost increases.